接口单元不支持系统verilog(Interface cell not supported system verilog)

接口单元不支持系统verilog(Interface cell not supported system verilog)

我在尝试编译一些文件时遇到此错误。

错误 - [NYI-NS]尚未实现尚不支持以下功能：更换尚未支持的逻辑库中的接口单元

我的文件：monitor_interface.sv

interface monitor_if( input logic a, input logic b ); endinterface bind TB monitor_if mon_if1( ... );

文件2（具有“include monitor_interface.sv”）

virtual monitor_if if1; //passes this interface to another module.

我不明白发生了什么。 任何指针都将非常感激。

[编辑] top.sv

virtual monitor_interface monitor_if; initial begin ... end monitor mon1(monitor_if);

monitor.sv：

module monitor (monitor_if);

I am getting this error while trying to compile some files.

Error-[NYI-NS] Not Yet Implemented The following feature is not yet supported: Replacing interface cell in logical library not yet supported

My files: monitor_interface.sv

interface monitor_if( input logic a, input logic b ); endinterface bind TB monitor_if mon_if1( ... );

File 2 (which has "`include monitor_interface.sv")

virtual monitor_if if1; //passes this interface to another module.

I don't understand what is going on. Any pointers will be much appreciated.

[Edit] top.sv

virtual monitor_interface monitor_if; initial begin ... end monitor mon1(monitor_if);

monitor.sv:

module monitor (monitor_if);

最满意答案

“尚未实现”消息通常意味着该工具会识别您要执行的操作，但不支持它，很可能与绑定构造有关。 你应该得到一个指向确切位置的行号。

绑定语句是否在另一个模块中？ 或任何结构之外。

问题也可能是你在某个地方犯了错误，编译器做了最好的理解，但它给你一个无关的错误。 `include语句在哪里？

A "Not Yet Implemented" message usually means the tool recognizes what you are trying to do, but does not support it, most likely related to the bind construct. You should have gotten a line number pointing to the exact spot.

Is the bind statement inside another module? or outside of any construct.

The problem could also be you made a mistake somewhere and the compiler did the best it could do understand, but it is giving you an unrelated error. where is the `include statement?

接口单元不支持系统verilog(Interface cell not supported system verilog)

我在尝试编译一些文件时遇到此错误。

错误 - [NYI-NS]尚未实现尚不支持以下功能：更换尚未支持的逻辑库中的接口单元

我的文件：monitor_interface.sv

interface monitor_if( input logic a, input logic b ); endinterface bind TB monitor_if mon_if1( ... );

文件2（具有“include monitor_interface.sv”）

virtual monitor_if if1; //passes this interface to another module.

我不明白发生了什么。 任何指针都将非常感激。

[编辑] top.sv

virtual monitor_interface monitor_if; initial begin ... end monitor mon1(monitor_if);

monitor.sv：

module monitor (monitor_if);

I am getting this error while trying to compile some files.

Error-[NYI-NS] Not Yet Implemented The following feature is not yet supported: Replacing interface cell in logical library not yet supported

My files: monitor_interface.sv

interface monitor_if( input logic a, input logic b ); endinterface bind TB monitor_if mon_if1( ... );

File 2 (which has "`include monitor_interface.sv")

virtual monitor_if if1; //passes this interface to another module.

I don't understand what is going on. Any pointers will be much appreciated.

[Edit] top.sv

virtual monitor_interface monitor_if; initial begin ... end monitor mon1(monitor_if);

monitor.sv:

module monitor (monitor_if);

最满意答案

“尚未实现”消息通常意味着该工具会识别您要执行的操作，但不支持它，很可能与绑定构造有关。 你应该得到一个指向确切位置的行号。

绑定语句是否在另一个模块中？ 或任何结构之外。

问题也可能是你在某个地方犯了错误，编译器做了最好的理解，但它给你一个无关的错误。 `include语句在哪里？

A "Not Yet Implemented" message usually means the tool recognizes what you are trying to do, but does not support it, most likely related to the bind construct. You should have gotten a line number pointing to the exact spot.

Is the bind statement inside another module? or outside of any construct.

The problem could also be you made a mistake somewhere and the compiler did the best it could do understand, but it is giving you an unrelated error. where is the `include statement?